1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including an output circuit capable of switching output impedances.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), impedances of an output circuit are required to be variable. Preparing plural output buffers having different impedances is considered to meet the requirement. However, in this case, a circuit scale of output circuits as a whole becomes very large, and a calibration circuit is necessary for each output buffer.
To solve the above problem, plural unit buffers each having the same impedance are prepared in advance, and the number of unit buffers to be used in parallel is selected according to an assigned impedance, instead of preparing plural output buffers having different impedances. According to this method, ideally, an output impedance can be set at X/i (i is an integer of 1 to n) by selecting one or more output buffers among n buffers in parallel, where X represents an impedance of one unit buffer (see Japanese Patent Application Laid-open No. 2008-60679 filed by the assignee of the present invention).
In a semiconductor device described in Japanese Patent Application Laid-open No. 2008-60679, impedances of unit buffers are collectively adjusted by a calibration circuit.
Specifically, a voltage at a calibration terminal and a reference voltage are compared with each other in case where an external resistor is connected to the calibration terminal, thereby adjusting an impedance of a replica buffer. Impedances of unit buffers can be collectively set by reflecting adjusted impedances of the replica buffer to each unit buffer.
Japanese Patent Application Laid-open No. 2008-60679 proposes a method of decreasing a deviation of impedance attributable to a parasitic resistance between a power source terminal and a unit buffer. A parasitic resistance is present between an output terminal and each unit buffer as well as between the power source terminal and each unit buffer. However, the parasitic resistance between the output terminal and each unit buffer is smaller than that between the power source terminal and each unit buffer, and thus conventionally it has not been a serious problem.
However, higher impedance precision has been required in recent years, and deviation of impedance attributable to a parasitic resistance between an output terminal and a unit buffer needs to be decreased. In this respect, employing the same method as that of Japanese Patent Application Laid-open No. 2008-60679 is not necessarily the best way, because a part of output wirings that connect an output terminal and a unit buffer is formed in a lower wiring layer where a resistance value is relatively high, while a major part of power source wirings is formed in a top low-resistance wiring layer.